Due to the high degree of integration of electronic circuits, the frequency of errors is increasing. It is known to monitor digital circuits for example by duplication and comparison, by using codes and generally by means of error detection circuits (cf. Goessel et al. “Error Detecting Circuits”, McGrawHill, 1994; Rao et al. “Error Control Coding for Computer Systems”, Prentice Hall, 1989).
An error detection circuit is used to detect an error in the circuit to be monitored. If errors occur relatively frequently in electronic circuits, then it is particularly disadvantageous that the errors cannot be corrected by the error detection circuit, and therefore the circuit is relatively often not capable of functioning due to its errors.
It is also known to use error-correcting circuits to correct the errors which occur. For instance, it is known to design error-correcting circuits through system triplication and one or more subsequent voters and on the basis of error-correcting codes (cf. Lala, P. K., “Self-Checking and Fault-Tolerant Digital Design”, Morgan Kaufman Publishers, San Francisco, 2001). One particular disadvantage here is the fact that the necessary hardware complexity is high and that only relatively few errors can be corrected when using an error-correcting code.
Due to the high degree of integration of electronic circuits, the susceptibility to errors and the frequency of errors is increasing with regard to non-permanent or transient errors. These errors may lead to “soft errors” in the memory elements.
Electronic digital circuits generally consist of a combinatorial circuit part and memory elements which can be formed as latches or as flip-flops. If a transient error occurs in the combinatorial circuit part, then logical, electrical and temporal conditions have to be met simultaneously (cf. Liden et al. “On Latching Probability of Particle Induced Transients in Combinational Networks”, Proc. Int. Symp. On Fault-Tolerant Computing, pages 340-349, 1994) so that such an error can act as a soft error in a memory element.
More frequently, a soft error occurs in a memory element directly, wherein the memory element may be a latch or a flip-flop, such an error being caused for example by radiation. The occurrence of soft errors in latches or flip-flops is known and is described for example in Buchner et al. “Comparison of Error Rates in Combinational and Sequential Logic”, IEEE Trans. Nucl. Science. vol. 44, pages 2209-2216, 1997. It is known that the sensitivity of a latch or flip-flop with regard to the occurrence of a soft error depends on the value of the clock signal clock. If, for example, clock=1, then the data input of the latch or flip-flop determines the state of the memory element and the memory element is immune to soft errors. If clock=0, then the state of the memory element is decoupled from the data input and the state of the latch or flip-flop is sensitive to soft errors. If in a memory element, therefore, a soft error occurs which has been produced in the memory element for example by radiation, then the state of the memory element is correct for the value clock=1 of the clock signal and is incorrect for the value clock=0 of the clock signal.
In one clock cycle, the clock signal changes from 1 to 0. The state for a soft error caused in the memory element is therefore correct in the first half of the cycle and incorrect in the second half of the cycle. If, on the other hand, a transient error exists in the combinatorial circuit part and the logical, electrical and temporal conditions are met, then the incorrect data input at the input of a memory element is accepted by the memory element and the state of the memory element is incorrect for the entire cycle.
C-elements are known in various embodiments and implementations (cf Muller et al., “A Theory of Asynchronous Circuits”, Proc. Int. Symp. on the Theory of Switching, pages 2004-43, Harvard Univ. Press, 1959; Shams et al. “Optimizing CMOS Implementations of the C-element”, Proc. ICCD 97, pages 700-705, 1997; “Modeling and Comparison CMOS Implementations of the C-Element, Trans. VLSI-Systems, vol. 6, pages 563-567, 1998). In order to improve the electrical properties of C-elements, for example in order to avoid quiescent currents, in particular the output of the C-element can be designed differently. Since the design of different C-elements is known per se to the person skilled in the art, it is not necessary to discuss this in any further detail here.
The C-element usually has two inputs and one output. If the two input values are the same, it outputs its input value. If its two input values are not the same, it outputs the previous value. A C-element with a plurality of inputs has been used for error detection (cf. Kundu et al. “Self-Checking Komparator with One Periodic Eingang, IEEE Trans. Comp. vol. 45, pages 379-380, 1996). The C-element can therefore be used to correct soft errors which have been produced in the memory elements if the memory elements are duplicated. The inputs of a C-element with two inputs are connected in this case to the two outputs of duplicate memory elements. If the outputs of the duplicate memory elements are the same, the same output value is output at the output of the C-element. If the two outputs of the two memory elements are different, the C-element outputs the previous value.
If a soft error is caused in one of the two memory elements for example by radiation, then the state of said one memory element changes only for the value clock=0 of the clock signal. The outputs of the two memory elements then correspond for the value clock=1 of the clock signal, whereas they differ for the value clock=0 of the clock signal. At the output of the C-element, the value applied to the input of the memory elements at the time at which the clock signal is 1 is output, and the present soft error caused in one of the memory elements for example by radiation is corrected.
In Mitra et al. (“Logic Soft-Errors a Major Barrier to Robust Platform Design”, Proc. ITC 2005, paper 28.5), circuits are considered which have special redundancy for the functional test, for the scan test and for debugging and which are operated in various modes. Special memory elements, so-called scan-out flip-flops, are used for building the circuits. For such circuits, the detection of soft errors, which have been caused exclusively in latches of these special memory elements, and the correction of soft errors, which have likewise been caused in latches of these special memory elements, is described by the XOR linking of the outputs of two latches of these memory elements and by the addition of a C-element.
It can be seen that the memory elements known as “scan-out flip-flops” are relatively complicated. They are operated in various modes which are selected via control lines and special control signals, which is complicated. For error detection, the solution proposed by Mitra et al. allows only the comparison or the XOR linking of the outputs of duplicate latches of the memory elements, wherein a certain mode has to be selected via a control line by a control signal. It can also be seen that only the errors which have been produced directly in a latch of a memory element, which is a “scan-out flip-flop”, can be detected in the described manner through the comparison or XOR linking of the outputs of duplicate latches of these memory elements. It is disadvantageous that errors in the combinatorial circuit parts of the circuit cannot be detected, since errors in the combinatorial circuit always lead to identical values in the duplicate latches of the memory elements. Errors in the corrected values further processed or output by the circuit and in the C-elements used also cannot be detected, so that the correctness of the corrected values cannot be checked, which is also disadvantageous.
A method for optimizing the transmission of data packets over a transmission channel is known from the document US 2006/0067531 A1. In particular, the document deals with the efficient transmission of the header of data packets. A method is proposed in which, between a transmitting device and a receiving device, a data packet is encrypted by means of a code selected from a plurality of encryption codes.